Sat, Dec 05, 2020

Prof. Chandan Giri, Department of Information Technology

Dr. Chandan Giri
it chandan Dr. Chandan Giri
Assistant Professor , Information Technology


  • Ph.D.

 

Contact Addresses
  Residence 45/54 B.G.Road, P.O. Botanic Garden, Howrah 711103, West Bengal, India
  Phone (office) +91 - 33 - 26684561/62/63 Ext. 858
  Mobile +91 - 9433255202
  email This e-mail address is being protected from spambots. You need JavaScript enabled to view it  

 

Research Areas
  • System-on-Chip Testing
  • 3D IC testing
  • Network-on-chip testing
  • Low power test

 

Recent Publications
  • Chandan Giri, B. Naveen Kumar and Santanu Chattopadhyay, “Scan Flip-Flop Ordering with Delay and Power Minimization During Testing”, Proc. IEEE Annual India Conference (INDICON), Chennai, pages: 467-471, December, 2005.
  • Chandan Giri, B. Mallikarjuna Rao and Santanu Chattopadhyay, “Test Data Compression using Huffman Coded Dictionary for System-On-Chip Testing”, Proc. Intl. Conference Electronic and Photonic Material, Devices and Systems (EPMDS) Kolkata, pages:I8-I10, January, 2006.
  • Chandan Giri, B. Mallikarjuna Rao and Santanu Chattopadhyay, “Reducing Power for System-On-Chip Testing”, Proc. Intl. Conference on Emerging Applications of IT (EAIT),Computer Society of India (CSI), Kolkata,February,2006.
  • Chandan Giri, Nikhil Reddy Cheruku and Santanu Chattopadhyay, “Test Vector Ordering for Power reduction During Transmission of compressed Test Patterns to Embedded System-On-Chip”, Proc. IEEE Annual India Conference (INDICON), New Delhi, pages:1-5, September, 2006.
  • Chandan Giri and Santanu Chattopadhyay, “Power Optimized Dictionary Coding for Test Data Compression”, Proc. IEEE Intl. Conference on Industrial Technology (ICIT), Bombay, pages: 2541-2545, December, 2006.
  • Chandan Giri, B. Naveen Kumar and Santanu Chattopadhyay, “Multiple Scan Chain Design for Power and Delay Minimization During Test”, Proc. Intl. Conference On Computers and Devices for Communication (CODEC), Kolkata, December, 2006.
  • Chandan Giri, B. Mallikarjuna Rao and Santanu Chattopadhyay, “Test Data Compression by Split-VIHC (SVIHC)”, Proc. Intl Conference on Computing: Theory and Applications (ICCTA), Kolkata, pp:146-150, March, 2007.
  • Chandan Giri, Dilip Kumar Reddy Tipparthi and Santanu Chattopadhyay, “Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling”, Proc. Intl Conference on Computing: Theory and Applications (ICCTA), Kolkata, pp:141-145, March, 2007.
  • Chandan Giri and Santanu Chattopadhyay, “Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs”, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA, pages:3679-3682, May, 2007.
  • Chandan Giri, Soumojit Sarkar and Santanu Chattopadhyay, “Test Scheduling for Core-based SOCs Using Genetic Algorithm based Heuristic Approach”, Proc. Intl. Conference on Intelligent Computing (ICIC), Qingdao, China, pages:1032-1041, August, 2007. Also as a book chapter in Lecture Notes in Computer science (LNCS), Springer, ISSN: 0302-9743 (Print) 1611-3349 (Online),Vol.4682/2007,ISBN:978-3-540-74201-2.
  • Chandan Giri, Nikhil Reddy Cheruku and Santanu Chattopadhyay, “Compression-Power Trade-off in Dictionary based Test Data Compression”, in Proc. IEEE VLSI Design And Test Symposium, Kolkata, August, 2007.
  • Chandan Giri, Pradeep Kumar Choudhary and Santanu Chattopadhyay, “Scan Architecture Modification with Test Vector Re-ordering for Test Power Reduction”, Proc. IEEE International Symposium on Integrated Circuits (ISIC), Singapore, September, 2007.
  • Chandan Giri, Pradeep Kumar Choudhary and Santanu Chattopadhyay, “Scan Power Reduction through Scan Architecture Modification and Test Vector Reordering”, in Proc. IEEE Asian Test Symposium, Beijing, China,pages:419-424, October, 2007.
  • Chandan Giri, Soumojit Sarkar and Santanu Chattopadhyay, “A Genetic Algorithm Based Heuristic Technique for Power Constrained Test Scheduling in Core-based SOCs”, Proc. IFIP Intl. Conference on Very Large Scale Integration (VLSI) SOC, Atalanta, USA, October, 2007.
  • Chandan Giri, Dilip Kumar Reddy Tipparthi and Santanu Chattopadhyay, “A Genetic Algorithm based Approach for System-on-Chip Test Scheduling using Dual Speed TAM with Power Constraint”, WSEAS Transactions on Circuits and Systems, Issue 5, Volume 7, pp: 416- 427, May 2008  

 

Courses Undertaken
  • Software Engineering
  • System Programming
  • Computer Graphics



Department of Information Technology, BESU, Shibpur - 7111 03, INDIA