Sat, Dec 05, 2020

Prof. Hafizur Rahman, Department of Information Technology

Dr. Hafizur Rahaman
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Dr.Hafizur Rahaman
Professor, Information Technology

  • B.E.(Electrical Engg.), B.E.College, Shibpur (Calcutta University)
  • M.E.(Electrical Engg.), Jadavpur University, Kolkata
  • PhD.(Computer Science and Engineering), Jadavpur University, Kolkata
  • Post Doc, University of Bristol, United Kingdom


Contact Addresses

Flat-2A, Block-3, Surya Niwas 5B Tiljala Road,Kolkata-700046,West Bengal, India

Phone (office)

Phone (Office):+91-33-26684561/62/62   Ext.309/249, Fax:-+91-33-26682916

Mobile +91 -9836533802
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Research Areas
  • Logic Synthesis
  • VLSI Design and Test
  • CAD for Microfluidic Biochips
  • Nanotechnology
  • Reversible Computing


Recent Publications
  • ManodipanSahoo, PrasunGhosal and, HafizuRahaman,“Modeling and Analysis of Cross talk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects: An ABCD Parameter Based Approach”, IEEE Transactions on Nanotechnology, (Accepted) 2014 (With PhD Student).
  • KamalikaData, I.Sengupta, HafizurRahaman and Rolf Drechsler, “An Approach to Reversible Logic Synthesis using Input and Output Permutations”, Springer Transactions on Computation Science XXIV, LNCS 8911, pp.1-8, 2014 (With PhD Student) (DOI:- 978-3-662-45710-8, 332808_1_En).
  • ChandanBandyopadhyay, HafizurRahamanand Rolf Drechsler, “Cube List based Cube Pairing Approach for Synthesis of ESOP based Reversible logic”, Springer Transactions on Computational Science, XXIV, LNCS 8911, pp. 1–18, 2014, DOI: 10.1007/978-3-662-45711-5_8, (With PhD Student).
  • ManodipanSahoo and HafizurRahaman, “Modeling of Crosstalk Induced Effects in Copper Based Nano-Interconnects:An ABCD Parameter Matrix Based Approach”, Journal of Circuits, Systems, and Computers, Vol. 24, No. 2 (2015) 1540007, World Scientific Publishing Company, DOI: 10.1142/S0218126615400071, (With PhD Student).
  • ManodipanSahoo,HafizurRahaman and BhargabB.Bhattacharya, “On the Suitability of Single-Walled Carbon Nanotube Bundle Interconnects for High-Speed and Power Efficient Applications”,Journal of Low Power Electronics, American Scientific Publishers, Vol. 10, No 3, pp. 479-494, September 2014. (With PhD Student). (DOI: 10.1166/jolpe.2014.1339)
  • KamalikaDatta, BhadreshwarGhuku, IndranilSengupta, HafizurRahaman and Rolf Drechsler, “Synthesis of Reversible Logic Circuits using the Algebra of Permutation Cycles with Input/Output Orderings”,Journal of Circuits, Systems & Signal Processing, Springer publication (Accepted). (With PhD Student)
  • ManodipanSahoo, PrasunGhosal and HafizurRahaman, “Performance Modeling and Analysis of Carbon Nanotube Bundles for Future VLSI Circuit Applications", Journal of Computational Electronics, Springer Publication, pp.673-688, DOI 10.1007/s10825-014-0587-7, (With PhD Student) .
  • KamalikaDatta, GauravRathi, IndranilSengupta and HafizurRahaman,“An Improved Reversible Circuit Synthesis Approach using Clustering of ESOP Cubes”, ACM Journal on Emerging Technologies in Computing Systems (JETC), 11(2):15(2014), (With PhD Student).
  • KamalikaDatta, IndranilSengupta, and HafizurRahaman,“A Post-Synthesis Optimization Technique forReversible Circuits Exploiting Negative Control Lines”, IEEE Transactions on Computers 2014, (online available) (DOI:-I:10.1109/TC.2014.2315641), (With PhD Student)
  • Nachiketa Das, Pranab Roy, and HafizurRahaman, “Bridging Fault Detection in Cluster Based FPGA by Using Muller C Element”, Computers & Electrical Engineering (Elsevier), Vol. 39, Issue 8, November 2013, pp. 2469–2482. (With PhD Student). (DOI:10.1016/j.compeleceng.2013.08.009)
  • Nachiketa Das , Pranab Roy and HafizurRahaman, “Built-In-Self-Test Technique for Diagnosis of Delay Faults in Cluster Based Field Programmable Gate Arrays”, IET Computers & Digital Techniques,Vol.7, Issue 5, September 2013, pp.201-220. (With PhD Student). (DOI 10.1049/iet-cdt.2012.0111)
  • KamalikaDatta, IndranilSengupta, and HafizurRahaman, “A Particle Swarm Optimization based ReversibleCircuit Synthesis”, Journal of Low Power Electronics, Vol. 9 No. 3, pp.363-372, October 2013. (With PhD Student). (DOI:
  • Dipak K. Kole, HafizurRahaman, Debesh K. Das, and Bhargab B. Bhattacharya, “Derivation of Test Set for Detecting Multiple Missing-Gate Faults in Reversible Circuits”, Computer and Electrical Engineering (Elsevier), vol.39 (2), pp. 225-236, 2013 (With PhD Student). (DOI:10.1016/j.compeleceng.2012.11.016)
  • Debaprasad Das and HafizurRahaman, “Modeling of Single-Wall Carbon Nanotube Interconnects for Different Process, Temperature, and Voltage Conditions and Investigating Timing Delay”, Journal of Computational Electronics (Springer), Volume 11, Issue 4 (2012), pp. 349-363. (With PhD Student). (DOI 10.1007/s10825-012-0415-x)
  • Pranab Roy, HafizurRahaman and ParthasarthiDasGupta, “Two-level Clustering-based Techniques for Intelligent Droplet Routing in Digital Microfluidic Biochips”, Integration, the VLSI Journal(Elsevier), Vol.45, issue 3, June 2012, pp.316-330. (With PhD Student). (DOI:10.1016/j.vlsi.2011.11.006)
  • Debaprasad Das and HafizurRahaman,"Crosstalk Overshoot/undershoot Analysis and its impact on Gate Oxide Reliability in Multi-wall Carbon Nanotube Interconnects”, Journal of Computational Electronics (Springer), 2011, Volume 10, Number 4, pp..360-372. (With PhD Student). (DOI 10.1007/s10825-011-0371-x)
  • DebasisMitra, SarmishthaGhoshal, HafizurRahaman, Bhargab B Bhattacharya, KrishnenduChakraborty, ‘Test Planning in Digital Microfluidic Biochips using Efficient Eulerization Techniques’, International Journal of Electronic Testing: Theory and Applications (JETTA), 2011, pp.657-671. . (With PhD Student). (DOI: 10.1007/s10836-011-5239-2)
  • Debaprasad Das and HafizurRahaman,"Analysis of Crosstalk in Single- and Multi-Wall Carbon Nanotube Interconnects and its Impact on Gate Oxide Reliability", IEEE Transactions on Nanotechnology, vol. 10, no. 6, pp. 1362-1370, Nov. 2011 (With PhD Student). (DOI:10.1109/TNANO.2011.2146271)
  • HafizurRahaman, Dipak K. Kole, Debesh K. Das, Bhargab B. Bhattacharya, “Fault Diagnosis for Missing-Gate Fault (SMGF) Model in Reversible Quantum Circuits”, International Journal of Computer and Electrical Engineering (Elsevier),vol. 37 (2011) 475–485. (With PhD Student). (DOI:10.1016/j.compeleceng.2011.05.005)
  • T. Samanta, H. Rahaman, P. Dasgupta, “Near-optimal Y-routed delay trees in nanometric interconnect design “,IEE Computers and Digital Techniques, 2011, vol. 5(1), pp. 36 – 48. ). (with PhD student).(DOI:10.1049/iet-cdt.2009.0074)
  • HafizurRahaman, Jimson Mathew and Dhiraj K. Pradhan, “Test Generation in Systolic Architecture for Multiplication over GF(2m)”, IEEE Transactions on VLSI Systems, volume 18, issue 9, pp.1366-1371, 2010 ( DOI:10.1109/TVLSI.2009.2023381). (DOI:10.1109/TVLSI.2009.2023381)
  • Somsubhra Talapatra and HafizurRahaman, “Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF(2m)”, IEEE Transactions on VLSI Systems, vol.18, issue 5, pp.847-852, 2010.(DOI:10.1109/TVLSI.2009.2016753)
  • J. Mathew, H. Rahaman, and D. K. Pradhan, “A Galois Field Based Logic Synthesis Approach with Testability”, IET Computers & Digital Techniques, Vol.4, issue 4, pp.263 – 273, 2010. (DOI:10.1109/VLSI.2008.88)
  • HafizurRahaman, Jimson Mathew and Dhiraj K. Pradhan, “Simplified Bit Parallel Systolic Multipliers for Special Class of GF(2m) with Testability”, IEE Computers and Digital Techniques, Vol.4, issue 5, pp. 428-437, 2010. (DOI:10.1049/iet-cdt.2009.0068)
  • H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Testable Design of AND-EXOR Logic Networks with Universal Tests for Detecting Stuck-at and Bridging Faults,” Journal of Computers and Electrical Engineering (Elsevier),vol.35, pp.644-658, DOI: 10.1016/j.compeleceng.2009.01.006.
  • H. Rahaman, J. Mathew, A. M. Jabir and D. K. Pradhan, “C-Testable Bit Parallel Multipliers over GF(2m)”, ACM Transactions on Design Automation of Electronic Systems, Vol. 13, No. 1, Article 5, January 2008. (DOI:10.1145/1297666.1297671)
  • H. Rahaman, J. Mathew, A. M. Jabir and D. K. Pradhan, “Derivation of Reduced Test Vectors to Test Bit Parallel Multipliers over GF(2m)”, IEEE Transactions on Computers, Vol.57, No.9, pp.1289-1294, September 2008. (DOI: 10.1109/TC.2008.63)
  • H. Rahaman, D. K. Das, and B. B. Bhattacharya, “An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Complex Cell,” IEEE Transactions on Instrumentation and Measurement, Vol. 57, No. 12, pp.2838-2845, December 2008. (DOI: 10.1109/TIM.2008.926414)


Courses Undertaken
  • Digital Logic and Circuit Design
  • Microprocessors and Microcontrollers
  • Advanced Computer Architecture
  • VLSI Testing
  • Advanced System Architecture


Department of Information Technology, BESU, Shibpur - 7111 03, INDIA